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PRELIMINARY
Differential Hall Sensor
TLE4925/TLE4925C
Features * * * * * * * * * * * * * * * * *
Advanced performance by dynamic self calibration principle High sensitivity Single chip solution Symmetrical thresholds High resistance to Piezo effects South and north pole pre-induction possible low cut-off frequency Digital output signal Two-wire and three-wire configuration possible Wide operating temperature range Fast start-up time Large operating air-gaps Reverse voltage protection at Vs- PIN Short- circuit and over temperature protection of output No external filter capacitor required (TLE4925C) Digital output signal (voltage interface) Module style package with two 4.7nF integrated capacitors (TLE4925C)
Page 1 of 25
PRELIMINARY
P-SSO-3-6
P-SSO-3-9
123
123
Figure 1: Pin configuration in P-SSO-3-6 and P-SSO-3-9
Pin No. 1 2 3
Symbol VS GND Q
Function Supply Voltage Ground Open Drain Output
General Information The TLE4925/TLE4925C is an active Hall sensor suited to detects the motion and position of ferromagnetic and permanent magnet structures. An additional selfcalibration module has been implemented to achieve optimum accuracy during normal running operation. It comes in a three-pin package for the supply voltage and an open drain output. Functional Description The differential Hall sensor IC detects the motion and position of ferromagnetic and permanent magnet structures by measuring the differential flux density of the magnetic field. To detect ferromagnetic objects the magnetic field must be provided by a back biasing permanent magnet (south or north pole of the magnet attached to the rear unmarked side of the IC package).
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PRELIMINARY
Offset cancellation is achieved by advanced digital signal processing. Immediately after power-on motion is detected (start-up mode). After a few transitions the sensor has finished self-calibration and switches to a high-accuracy mode (running mode). In running mode switching occurs at signal zero-crossing of the arithmetic mean of max and min value of magnetic differential signal. B is defined as difference between hall plate 1 and hall plate 2.
Q VS clamping & reverse voltage protection hyst comp overtemperature & short-circuit protection clamping
power supply regulator analog supply digital supply main comp enable
n-channel open drain
interface Hall probes
++ + amplifier -Offset DAC
filter
Tracking ADC
digital min max algorithm
actual switching level bias for temperature & technology compensation
oscillator
GND
reset
Figure 2: Block Diagram of TLE4925/TLE4925C
Circuit Description The TLE4925/TLE4925C is comprised of a supply voltage regulator, a pair of hall probes, spaced at 2.5mm, differential amplifier, noise-shaping filter, comparator, advanced digital signal processor (DSP), A/D and D/A converter and an open drain output. Startup mode: The differential signal is digitized in the A/D converter and fed into the dsp part of the circuit. There a rising or falling transition is detected and the output stage is triggered accordingly. As the signal is not offset compensated at this time, the output does not neccessarily switch at zero-crossing of the magnetic signal. Signal peaks are also detected in the digital circuit and their arithmetic mean value can be calculated. The offset of this mean value is determined and fed into the offset cancellation DAC. This procedure can be repeated with increasing accuracy. After few increments the IC is switched into the high accuracy running mode.
Page 3 of 25
PRELIMINARY
Running mode: In running mode the output is triggered by the comparator. An offset cancellation feedback loop is formed by the A/D converter, dsp and offset cancellation D/A converter. In running mode switching always occurs at zero-crossing. It is only affected by the (small) remaining offset of the comparator and by the remaining propagation delay time of the signal path, mainly determined by the noise-shaping filter. Nevertheless signals below a defined threshold are not detected to avoid unwanted parasitic switching.
peak detection offset= (max + min) / 2
offset
offset correction
startup-mode
running-mode
Figure 3: Startup of the device At transition from startup-mode to running mode switching timing is moving from low-accuracy to high accuracy zero-crossing.
Page 4 of 25
PRELIMINARY
1.1 Absolute Maximum Ratings
No. 1.1.1 Parameter Supply voltage Symbol VS min -18 -24 -26 -28 1.1.2 1.1.3 Supply current Output OFF voltage IS VQ -10 -0.3 -0.3 -0.3 -1.0 Typ max 18 24 26 28 25 18 24 26 Unit V V V V mA V V V V 1h with RSeries 2001 5min with RSeries 2001 1min with RSeries 2001 1h with RLoad 500 5min with RLoad 500 1h (protected by internal series resistor) 1.1.4 Output ON voltage VQ 16 V Current internal limited by short circuit protection (72h @ TA < 40C). 18 V Current internal limited by short circuit protection (1h @ TA < 40C). 24 V Current internal limited by short circuit protection (1min @ TA < 40C). 1.1.5 Continuous output current 1.1.6 Junction temperature Tj -40 155 165 175 195 C C C C C 2000h (not additive) 1000h (not additive) 168 h (not additive) 3 x1 h (additive to the other life times). 1.1.7 1.1.8 Storage temperature Thermal resistance junction-air for P-SSO-3-6 P-SSO-3-9 TS Rth JA -40 150 190 C K/W Lower values are possible with overmoulded devices. IQ -50 50 mA Remarks
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Accumulated life time. Page 5 of 25
PRELIMINARY
1.2 Electro Magnetic Compatibility - (values depend on R Series!)
Ref. ISO 7637-1; see test circuit of figure 4 and 5; BPP = 10mT (ideal sinusoidal signal); VS=13.5V 0.5V, fB= 1000Hz; T= 25C; RSeries 200; No. 1.2.1 Parameter Testpulse 1 Testpulse 2 Testpulse 3a Testpulse 3b Testpulse 4 Testpulse 5 Symbol VEMC Level/typ IV / -100V IV / 100V IV / -150V IV / 100V IV / -7V IV / 86.5V Status C2 C2 A A A C
Note: Test criteria for status A: No missing pulse no additional pulse on the IC output signal plus duty cycle and jitter are in the specification limits. Test criteria for status B: No missing pulse no additional pulse on the IC output signal. (Output signal "OFF" means switching to the voltage of the pull-up resistor). Test criteria for status C: One or more parameter can be out of specification during the exposure but returns automatically to normal operation after exposure is removed. Test criteria for status E: IC destroyed.
Ref. ISO 7637-3; TP 1 and TP 2 ref. DIN 40839-3; see test circuit of figure 4 and 5; BPP = 10mT (ideal sinusoidal signal); VS=13.5V 0.5V, fB= 1000Hz; T= 25C; RSeries 200; No. 1.2.2 Parameter Testpulse 1 Testpulse 2 Testpulse 3a Testpulse 3b Symbol VEMC Level/typ IV / -30V IV / 30V IV / -60V IV / 40V Status A A A A
Ref. ISO 11452-3; see test circuit of figure 4 and 5; measured in TEM-cell; BPP = 4mT (ideal sinusoidal signal); VS=13.5V 0,5V, fB= 200Hz; T= 25C; RSeries 200; No. 1.2.3 Parameter EMC field strength Symbol ETEM-Cell Level/max IV / 200V/m Remarks AM=80%, f=1kHz;
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Test condition for the trigger window: f -field=200Hz, Bpp=4mT, vertical limits are 200mV and B horizontal limits are 200s.
2
According to 7637-1 the supply switched OFF" for t=200ms. For battery ON" is valid status A". Page 6 of 25
PRELIMINARY
1.3 ESD Protection
No. 1.3.1 Parameter ESD - protection P-SSO-3-9 P-SSO-3-6 VESD 8 6 kV kV Symbol max Unit Remarks According to standard EIA/JESD22-A114-B Human Body Model (HBM).
5V RSeries 200 CInt-package VEMC VS GND CInt-package Q 4.7 nF CLoad 50 pF
RLoad 4.7 nF
1.2 k
Figure 4: Test Circuit for EMC tests (TLE4925C) - P-SSO-3-9 Package
5V RSeries 200 4.7nF VEMC CExt1 VS GND Q CLoad 50pF CExt2 4.7nF RLoad
1.2k
Figure 5: Test Circuit for EMC tests (TLE4925) - P-SSO-3-6 Package
Page 7 of 25
PRELIMINARY
2.1 Operating Range
No. 2.1.1 Parameter Supply voltage Symbol VS min 3.3 typ max 18 24 26 Unit V V V Remarks Continuous 1h with RSeries 200 5min with RSeries 200. Extended limits for parameters in characteristics. 3 2.1.2 2.1.3 Supply voltage ripple Continuous output OFF voltage 2.1.4 Continuous output ON current 2.1.5 Power on time ton 1 ms Time to achieve specified accuracy After power on the output of the IC is always in high-state. After internal resets output is locked3. 2.1.6 Operating junction temperature Tj -40 155 165 175 C C C C 2000 h (not additive) 1000 h (not additive) 168 h (not additive) reduced signal quality permittable (e.g. jitter) Note: Unless otherwise noted, all temperatures refer to junction temperature. For the supply voltage lower than 28V (RSeries 200) and junction temperature lower than 195C the magnetic and AC/DC characteristics can exceed the specification limits. IQ VSAC VQ -0.3 -18 0 6 18 24 20 V Vpp V V mA During test pulse 4. VS=13V; 0 < f < 50kHz Continuous 1h with RLoad 500 VQmax=0.6V
3
Output of the IC is locked in present state (high-state or low-state) after an internal reset is launched. This reset happens typically every 780ms when there is no significant signal change. See also 2.2.14. A voltage reset causes a release of the output and output is in high state after power on again. Page 8 of 25
PRELIMINARY
2.2 AC/DC Characteristics
Over operating range, unless otherwise specified. Typical values correspond to VS=12V and TA=25C No. 2.2.1 2.2.2 2.2.3 Parameter Supply current Supply current @ 3.3V Supply current @ 24V Symbol IS ISVmin ISmax min 3 3 3 typ 6.8 6.7 7 max 9 8 9.5 Unit mA mA mA VS=3.3V VS=24V RSeries 200 2.2.4 Output saturation voltage 2.2.5 2.2.6 Output leakage current Current limit for shortCircuit protection 2.2.7 Junction temperature limit for output protection 2.2.8 Output rise time TLE4925C (P-SSO-3-9) tr4 4 12 20 s VLoad = 4.5 to 24V RLoad = 1.2k; CLoad = 4.7nF included in package. TLE4925 (P-SSO-3-6) 4 12 20 s VLoad = 4.5 to 24V RLoad = 1.2k; CLoad = 4.7nF external capacitor. 2.2.9 Output fall time TLE4925C (P-SSO-3-9) tf5 0.5 0.65 0.9 1.15 1.3 1.65 s s VLoad = 5V VLoad = 12V RLoad = 1.2k; CLoad = 4.7nF included in package. TLE4925 (P-SSO-3-6) 0.5 0.65 0.9 1.15 1.3 1.65 s s VLoad = 5V VLoad = 12V RLoad = 1.2k; CLoad = 4.7nF external capacitor. Tprot 195 210 230 C IQleak IQshort 30 0.1 60 10 80 A mA VQ= 18V VQsat 0.25 0.6 V IQ= 20mA Remarks
4
value of capacitor: 4.7nF10%; (excluded drift due to temperature); ceramic: X7R; maximum voltage: 100V. Page 9 of 25
PRELIMINARY
2.2.10
delay time
td
7
12.5
18 20
6
s s
Only valid for Tj=25C. Valid for Tj=-40C till Tj=175C. Higher magnetic slopes and overshoots reduce td, because the signal is filtered internal.
2.2.11
Temperature drift of delay time of output to magnetic edge
td
-6
37
6
s
Time over specified temperature range; not additional to td
2.2.12 2.2.13 2.2.14 2.2.15
Frequency range Oscillator frequency Offset recalibration time after last output change Clamping voltage VS-Pin
f fOSC treset VSclamp
0.001 1.08 625 24 1.34 780 27.5
8 1.68 970
kHz MHz ms V
Operation below 1Hz 8 Output locked to state before recalibration IS = 20mA < 5min.
2.2.16 2.2.17 Note:
Clamping voltage Q- Pin Analog reset voltage
VQclamp VsReset
24
27.5 2.35 2.9
V V
IQ = 20mA < 5min. -
The listed AC/DC and magnetic characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not other specified, typical characteristics apply at Tj = 25 C and VS = 12 V.
2.3 Magnetic Characteristics in Running Mode
No. 2.3.1 2.3.2 2.3.3 Parameter Bias preinduction Differential bias induction Minimum signal amplitude 2.3.4 Maximum signal amplitude 2.3.5 Resistivity against mechanical stress (piezo) Bmin -0.2 0.2 mT F= 2N Bmax 100 mT Additional to B0 10 Symbol B0 B0 Bmin min -500 -30 0.55 typ max 500 30 1.5 Unit mT mT mT 9
Remarks
5 6
see footnote 6. only valid for the falling edge. 7 related to Tj= 175C. 8 output will switch if magnetic signal is changing more that 2xBmin within offset recalibration time even below 1Hz once per magnetic edge 9 includes also former Bm of TLE4941-2. 10 exceeding this limit might result in decreased duty cycle performance. With higher values the internal measured signal will be clipped. This will decrease the phase accuracy. Page 10 of 25
PRELIMINARY
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at Tj=25C and the given supply voltage.
3.1 Self-calibration Characteristics
No. 3.1.1 Parameter No. of transitions for signal output at startup (startup mode) 3.1.2 No. of transitions for entering running mode nCalib 7 Low accuracy of switching timing permitted 3.1.3 Duty cycle in running mode
11
Symbol nStart
min
typ
max 2
Unit -
Remarks
Dty
457
507
557
%
BPP = 10mT ideal sinusoidal input signal (Tj=25C)
407
507
607
%
BPP = 10mT ideal sinusoidal input signal (-40C Tj < 175C)
3.1.4
Signal jitter in running mode; 1 sigma value7
1
0.11
12
%
BPP = 10mT ideal sinusoidal input signal; Tj<150C
2
0.168
%
BPP = 10mT ideal sinusoidal input signal; 150C Tj < 175C
3.1.5
Signal Jitter in running mode at power supply of Vs=13V and ripple 3V; 1 sigma value*
3
0.11
%
BPP = 10mT ideal sinusoidal input signal; Tj<150C
11 12
this corresponds to a B0 = 0mT (magnetic offset). typical half value of TLE4941-2 performance (depends largely onBminand also on f). Page 11 of 25
PRELIMINARY
3.1.6
Effective noise value of the magnetic switching points
Bneff
25
T
Tj = 25C; The magnetic noise is normal distributed, nearly independent to frequency and without sampling noise or digital noise effects. The effective value corresponds to 1 probability of normal distribution. Consequently a 3 value corresponds to 0.3% probability of appearance.
70
T
Typical value corresponds to 1. Max value corresponds to 1 values in the full temperature range and include technological spreads.
3.1.7
Phase error in startup mode
55
BPP = 10mT ideal sinusoidal input signal;13
3.1.8
Frequency distribution of signal jitter
Jitter shall be distributed like white noise
-
13
smaller phase errors are possible at higher signal amplitudes, because sinus signal changes to a more rectangle signal. Page 12 of 25
PRELIMINARY
B Bmax
B 50% BPP
Bmin
BPP = 2 x B
B=B1-B2 (signal amplitude)
t
UQ
tr tf 90%
VQ-High
50%
td
VQ-Low
10% t1 T
t
Figure 6
Switching direction
Signal T
T
t
1... 3 =
1 1 (T ) 2 T ( n - 1)
measurement condition: n 1000
Figure 7
Definition of signal jitter
Page 13 of 25
PRELIMINARY
Application Configurations
Two possible applications are shown in Figure 8 and Figure 9 (Toothed and Magnet Wheel). The difference between two-wire and three-wire application is shown in Figure 12 for the TLE4925C and in Figure 13 for the TLE4925. Gear Tooth Sensing In the case of ferromagnetic toothed wheel application the IC has to be biased by the south or north pole of a permanent magnet (e.g. SmCO5 (Vacuumschmelze VX145)) with the dimensions 8 mm x 5 mm x 3 mm) which should cover both Hall probes. The maximum air gap depends on - the magnetic field strength (magnet used; pre-induction) and - the toothed wheel that is used (dimensions, material, etc.; resulting differential field).
a
centered distance of Hall probes b Hall probes to IC surface L IC surface to tooth wheel a = 2.5 mm b = 0.3 mm
S N
Figure 8
Sensor Spacing
Conversion DIN - ASA m = 25.4 mm/p T = 25.4 mm CP DIN d z m T ASA p diameter pitch p = z/d (inch) PD pitch diameter PD = z/p (inch) CP circular pitch CP = 1 inch x /p
diameter (mm) number of teeth module m = d/z (mm) pitch T = x m (mm)
Figure 9
Toothed Wheel Dimensions
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PRELIMINARY
Hall Sensor 1
N (S) S (N)
Figure 10
TLE4925/TLE 4925C, with Ferromagnetic Toothed Wheel
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PRELIMINARY
Figure 11
TLE4925/TLE 4925C, with Magnet Wheel
1 3 2
for example: RL=1,2k RS =120
1 3 2
for example: RP 200 RL=1,2k
Figure 12
Application Circuits TLE4925C
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PRELIMINARY
1 3 2
for example: RL=1,2k RS =120
1 3 2
for example: RP 200 RL=1,2k
Figure 13
Application Circuits TLE4925
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PRELIMINARY
S (N) N (S) Pin 3 (Q) B2 B1 Branded Side Crankshaft Wheel Profile Pin 1 (Vs)
Magnetic Field Difference B=B1-B2
Large airgap
Small airgap
BENOP=1mT Hidden Hysteresis BHYS=2mT
BENRP=-1mT
Output Signal VQ
Enabling point for releasing output: B1-B2>BENRP switches the output OFF (V Q=HIGH) Enabling point for operate point: B1-B2Figure 14
System Operation with hidden hysteresis
Page 18 of 25
PRELIMINARY
P-SSO-3-9 (Plastic Single Small Outline)
Figure 15
Package Dimensions (P-SSO-3-9)
Page 19 of 25
PRELIMINARY
Figure 16
Hall probe spacing in the P-SSO-3-9 package
Figure 17
Tape Loading Orientation in the P-SSO-3-9 package
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PRELIMINARY
Figure 18
Tape Loading Orientation in the P-SSO-3-6 package
Page 21 of 25
PRELIMINARY
Figure 19
Hall probe spacing in the P-SSO-3-6 package
Page 22 of 25
PRELIMINARY
Appendix:
Calculation of mechanical errors:
Magnetic Signal
Output Signal
Figure 20: Systematic Error and Stochastic Error

Systematic Phase Error
The systematic error comes in because of the delay-time between the threshold point and the time when the output is switching. It can be calculated as follows:
=
360 * n * td 60
n td
... systematic phase error in ... speed of the camshaft-wheel in min-1 ... delay time (see specification) in sec Page 23 of 25
PRELIMINARY
Stochastic Phase Error The stochastic phase error includes the error due to the variation of the delay time with temperature and the error caused by the resolution of the threshold. It can be calculated in the following way:
d =
360 * n * td 60
d n td
... stochastic phase error due to the variation of the delay time over temperature in ... speed of the camshaft wheel in min-1 ... variation of delay time over temperature in sec
Jitter (Repeatability)
B
B
Bdiff_max Bdiff_typ 1 3
Noise
The phase jitter is normally caused by the analogue system noise. If there is an update of the offset-DAC due to the algorithm, what could happen after each tooth, then an additional step in the phase occurs (see description of the algorithm). This is not included in the following calculations. The noise is transformed through the slope of the magnetic edge into a phase error. The phase jitter is determined by the two formulas:
Phase-Jitter
Figure17: Phase-Jitter
Jitter _ typ =
* (Bneff _ typ ) B
Jitter _ max =
* (Bneff _ max ) B
Page 24 of 25
PRELIMINARY
Jitter_typ Jitter_max ... B Bneff_typ Bneff_max
... typical phase jitter at Tj=25C in (1Sigma) maximum phase jitter at Tj=175C in (3Sigma) ... ... ... inverse of the magnetic slope of the edge in /T typical value of Bdiff in T (1-value at Tj=25C) maximum value of Bdiff in T (3-value at Tj=175C)
Example:
Assumption: n = 4500 min-1 td = 14 s td = 3 s B = 3 mT/ Bneff_typ = 40 T (1-value at Tj=25C) Bneff_max = 210 T (3-value at Tj=175C)
Calculation:
= 0.378 d = 0.081 Jitter_typ = 0.013 Jitter_max = 0.07
... ... ... ...
systematic phase error stochastic phase error due to delay time variation typical phase jitter (1-value at Tj=25C) maximum phase jitter (3-value at Tj=175C)
Page 25 of 25

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